Bit-Serial, VLSI Architecture for the Implementation of Maximum-Length Number-Theoretic Transforms Using Mixed Basis Represent at ions

Fermat and Mersenne N T T s are relatively easy to implement, but unsuitable for many DSP applications, due to small block length over wordlength. This paper presents VLSI design techniques appropriate for a wider range of N T T s , including maximum-length N T T s , and presents a systolic architecture exploiting blocklength factorisation to decompose the architecture into sub-modules, themselves systolic N T T s . The design avoids the explicit implementation of modular addition, accumulation and multiplication by using systolic basis converters which, inherently, perform the aforementioned tasks. The implementation of a maximum-length, 60pt N T T is described as an example. It uses binary to ternary basis conversion to perform all addition and multiplication, and 'ternary basis compression' to perf o r m accumulation.